This invention relates to programmable logic device integrated circuits and the like, all of which are referred to generically herein as PLDs. More particularly, the invention relates to high-speed serial interface (“HSSI”) circuitry for inclusion in PLDs.
There is increasing interest in using high-speed serial data signals for exchanging information between devices in various types of systems. The speeds (serial data rates) that are desired for such communication are constantly increasing, and the various protocols that may be used for such communication are also increasing in both number and sophistication. Some of these protocols use several serial data signals in a coordinated way (i.e., each serial data signal includes only part of the data being communicated). Some protocols require the use of cyclic redundancy check (“CRC”) technology.
It may be desired to use PLDs in systems employing high-speed serial data signals as described in the preceding paragraph. PLDs are relatively general-purpose devices that are capable of supporting any of many different possible uses. A PLD is programmed or “configured” to perform the operations that are required in a particular use. PLDs include general-purpose logic circuitry, which is typically the major portion of the device. Most of such “PLD core” circuitry is programmable to perform any of a wide range of possible logic tasks or the like (although PLD core circuitry may also include some relatively specialized circuitry such as blocks of random access memory (“RAM”), processor or microprocessor circuitry, digital signal processing (“DSP”) circuitry, etc., which is at least partly hard-wired to perform at least some particular functions). It is also known to include HSSI circuitry on PLDs to help the PLD support high-speed serial digital data communication. Again, such HSSI circuitry may be at least partly hard-wired to perform at least some functional aspects of the HSSI operation. The HSSI circuitry on a PLD may include a transmitter portion for accepting successive bytes or groups of bytes of parallel data (e.g., from the PLD core), serializing that data, and outputting the result as a high-speed serial data signal. Other operations (e.g., 8-bit-to-10-bit encoding) may also be performed on the data in the HSSI transmitter circuitry. Alternatively or in addition, the HSSI circuitry on a PLD may include a receiver portion for receiving a high-speed serial data signal, converting that data to successive bytes or groups of bytes of parallel data, and applying the parallel data to the PLD core. Again, other operations (e.g., 10-bit-to-8-bit decoding) may also be performed on the data in the HSSI receiver circuitry. If CRC operations are required in PLD implementations of high-speed data signaling, those operations have typically been performed in the general-purpose PLD core circuitry of the device.